As miniaturization of elements of an integrated circuit semiconductor device drives the industry, not only must critical dimensions of elements shrink, but also vertical variation or “topography” must be minimized in order to increase lithography and etch process windows and, ultimately, the yield of integrated circuits.
Conventional STI fabrication techniques include forming a nitride, e.g., silicon nitride, planarization stop layer on an upper surface of a semiconductor substrate, etching the stop layer and semiconductor substrate to form a trench in the semiconductor substrate, forming a thermal oxide liner in the trench and then filling the trench with isolation material, such as silicon oxide, forming an overburden on the nitride planarization stop layer. Planarization is then implemented, as by conducting chemical mechanical polishing (CMP). During subsequent processing, the nitride layer is removed followed by formation of active areas, which typically involve masking, ion implantation, and cleaning steps. During such cleaning steps, different species of oxide present in and one the various layers are removed at different rates, resulting in vertical variation in the isolation material. Further, a single species of oxide isolation material is removed at different rates depending on its location relative to other semiconductor device features. In other words, the oxide removal process and resulting isolation material stepheight are feature dependent. The vertical variation resulting from these factors inhibits the proper structure and encapsulation of any gate extending across an STI region, particularly as critical dimensions shrink.
Accordingly, it is desirable to provide methods for fabricating semiconductor devices with isolation regions having uniform stepheights. In addition, it is desirable to provide methods for fabricating semiconductor devices which utilize processes that are not feature dependent. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.